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DATA SHEET
Part No. Package Code No.
AN15865A
*QFH080-P-1420H
SEMICONDUCTOR COMPANY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Publication date: March 2004
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AN15865A Contents
Overview ............................................................................................................................ Features ............................................................................................................................. Applications ........................................................................................................................ Package ............................................................................................................................ Type .................................................................................................................................. Application Circuit Example .................................................................................................... Block Diagram ...................................................................................................................... Pin Descriptions ................................................................................................................... 3 3 3 3 3 4 5 7
Absolute Maximum Ratings .................................................................................................... 10 Operating Supply Voltage Range ............................................................................................. 10 Electrical Characteristics ....................................................................................................... 11 I2C Bus Conditions ............................................................................................................. 15
Test Circuit Diagram ............................................................................................................. 26 Technical Data ................................................................................................................... 27
1. Circuit diagrams of the input/output part and pin function descriptions ........................................... 27 2. Notes on video gain............................................................................................................. 35 3. Other supplementary matters................................................................................................. 35 Usage Notes ....................................................................................................................... 36
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AN15865A
AN15865A
The video switch IC including the synchronous separation function for TV
Overview
The AN15865A has the video switch portion which consists of a five-channel output in a ten-channel input, the synchronous separation function, the AFC function, and the format detection function. It contributes to the rationalization design of a television system.
Features
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Support multi scan / Auto format identification 480i, 576i, 480P, 576P, 720P, 1080i, 1152i, 1152i/letter (both 50 Hz & 60 Hz) Field 1 or 2 monitor out is available Auto distinction in the selected input (Sync on CV/Y or Sync on SY or no input signal) Dummy sync output 480i, 576i, 480P, 576P, 720P, 1080i (both 50 Hz & 60 Hz) Sync separation with AFC w/o external x-tal or clock 2 values, 3 values sync identification RGB YUV converter (CCIR standard, BTA standard, GBR matrix) Each output can be switched between LPF (6 MHz) & through Each output can be switched among 0 dB, 6 dB or mute Macrovision Comparators for Pin detection x4 (Connected / Open) Comparators for Aspect ratio x4 (4:3 video / 4:3 letter box / 16:9 video) High frequency (0 dB at 50 MHz) Support the I2C BUS Various input mode can be selected by using flexible internal switch OUTPUT CV1 CV2 CV3 CV4/SY4/SC4 CV5/SY5/SC5 CV6/SY6/SC6 CV7/SY7/SC7 Y7/U7/V7 Y6/U6/V6 Y5/U5/V5 Y4/U4/V4 Y3(G3)/U3(B3)/V3(R3) Y2(G2)/U2(B2)/V2(R2) Y1(G1)/U1(B1)/V1(R1) H6/V6 H5/V5 H4/V4 H3/V3 H2/V2 H1/V1
Note) *1: Independent HV only *2: Independent HV or Sync-separated HV
INPUT IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10
OUT1 CV1-7/SY4-7/ SC4-7 OUT2 CV1-7(SY4-7)/ SC4-7 OUT3 CV1-7(SY4-7)/ SC4-7 OUT4 OUT5 G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7) G(Y1-6)(CV1-7)/B(U1-6)(SY4-7)/ R(V1-6)(SC4-7) H1/V1 *1 H2/V2 *2
Applications
IC for Color TV
Package
80 Pin Plastic High Profile Quad Flat Package (QFP Type)
Type
Silicon Monolithic BICMOS IC
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AN15865A
Application Circuit Example
Input 6
Input 4
Input 3
Input 2
Input 1
Input 5
54 Y7/CV4
56 U7/SY4
46 Y6/CV5
60 Y5/CV6
62 U5/SY6
64 V5/SC6
44 U6/SY5
58 V7/SC4
63 Hin5
42 V6/SC5
49 GND1
43 Hin6
50 CV2
48 CV1
55 SA4
47 SA5
53 SB3
Input 6
Vin5 65 Y4/CV7 66 Hin4 67
57 SB4
41 Vin6 40 CV1 39 VCC2 38 SY1 37 DCOUT 36 SC1 10 k 9V Output 1 0.47 F 35 SLVADR 34 CV2/SY2 33 GND 32 SC2 31 GND2 30 CV3/SY3 29 GND 28 SC3 27 VCC3 26 G1/Y1 25 Hout1 5V Output 3 Output 2 B1/U1 24
52 CV3
51 SA3
59 SA6
61 SB6
Input 7
U4/SY7 68 Vin4 69 V4/SC7 70 9V VCC1 71
G3/Y3 72 Hin3 73 Input 8 B3/U3 74 Vin3 R3/V3 5V VCC4 G2/Y2 Hin2 Input 9 B2/U2 80 GND4 11 Sync-in 13 Vsyncsepa 14 R2/V2 16 Hout2 19 G2/Y2 20 GND3 21 R1/V1 22 4.7 F AFC1 10 Sync-out 12 0.022 F Field monitor 15 G1/Y1 5 B1/U1 7 B2/U2 18 R2/V2 2 R1/V1 9 Vout1 23 Vout2 17 SDA 3 Vin2 1 SCL 4 Hin1 6 Vin1 8 75 76 77 78 79
45 SB5
Output 4
0.01 F
4.7 k
75 k
Input 9 3.3 V Input 10
Output 5
Note : VCC1, VCC2 = 9 V 0.5 V VCC3, VCC4 = 5 V 0.3 V SLVADR : 5 V( 8Chex / 8Dhex ) 0 V( 84hex / 85hex )
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AN15865A
Block Diagram
(SYNC separation and AFC system)
Vin1 Vin2 Vin6 Hin1 Hin2
V Switch 1
Automatic Polarity control V1
( independent V )
Vout1
H Switch 1
Automatic Polarity control H1
( independent H )
Hout1
independent V (selected)
Hin6 Automatic Polarity control V2
V Counter Auto sync distinction
V Switch 2
( AFC-V or independent V )
Vout2
independent H (selected)
Automatic Polarity control H2 V Sync Separation V mask pulse Sync status Detector ( 2 or 3 ) H Counter
CV1 CV2 CV3 Y7/CV4 SY4 Y6/CV5 SY5 Y5/CV6 SY6 Y4/CV7 SY7 Y3 Y2 Y1
( AFC-H H or independent H ) Switch 2
Hout2
Switch
H Sync Separation
LOCK det Phase detector HVCO System mode control
clamp
MACRO VISION System status check
Sync-out
Sync-in
V sync sepa
AFC filter
Field monitor
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CV1
6/0 dB
LPF SY1
Sync-Sep
in1 in2 in3
6/0 dB
CV1 CV2 CV3 LPF SC1 LPF +
out1
in4
Y7/CV4 U7/SY4 V7/SC4
6/0 dB
6/0 dB
in5
6/0 dB
Y6/CV5 U6/SY5 V6/SC5 Hin6 Vin6 LPF
CV2/SY2
out2
+ SC2 LPF
in6
6/0 dB
Y5/CV6 U5/SY6 V5/SC6 Hin5 Vin5
6/0 dB
Sync-Sep
CV3/SY3 LPF
6/0 dB
in7
6/0 dB
Y4/CV7 U4/SY7 V4/SC7 Hin4 Vin4 +
SC3 LPF
out3
G1/Y1
G3/Y3 B3/U3
CCIR Matrix 2 BTA Matrix 3 GBR
6/0 dB
LPF B1/U1 6/0 dB LPF R1/V1 6/0 dB LPF
in8
R3/V3 Hin3 Vin3 G2/Y2
out4
in9
Vin2
B2/U2 R2/V2 Hin2
G2/Y2 G1/Y1 B1/U1 R1/V1 Hin1 Vin1 SA3 SA4 SA5 SA6 SB3 SB4 SB5 SB6 (Video-Switch) Switch
Hout1 Vout1
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CCIR Matrix 2 BTA Matrix 3
6/0 dB
LPF
in10
B2/U2
6/0 dB LPF
out5
R2/V2 Switch Through
GBR Sync-Sep 6/0 dB LPF
AFC Vref
Hout2 Vout2
AN15865A
Block Diagram (continued)
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AN15865A
Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin name Vin2 R2/V2 SDA SCL G1/Y1 Hin1 B1/U1 Vin1 R1/V1 AFC1 GND4 Sync-out Sync-in V sync sepa Field monitor R2/V2 Vout2 B2/U2 Hout2 G2/Y2 GND3 R1/V1 Vout1 B1/U1 Hout1 G1/Y1 VCC3 SC3 GND CV3/SY3 GND2 SC2 GND CV2/SY2 SLVADR Type In In In / Out In In In In In In In / Out Ground Out In In / Out Out Out Out Out Out Out Ground Out Out Out Out Out Independent V signal input 2 R2/V2 signal input I2C bus data input I2C bus clock input G1/Y1 signal input Independent H signal input 1 B1/U1 signal input Independent V signal input 1 R1/V1 signal input AFC filter Ground Sync signal output for sync separation Sync signal input for sync separation V sync separation filter Field change signal output R2/V2 signal output Independent V signal output 2 B2/U2 signal output Independent H signal output 2 G2/Y2 signal output Ground R1/V1 signal output Independent V signal output 1 B1/U1 signal output Independent H signal output 1 G1/Y1 signal output Description
Power supply 5.0 V power supply Out Ground Out Ground Out Ground Out In SC3 signal output Ground CV3/SY3 signal output Ground SC2 signal output Ground CV2/SY2 signal output Sets the I2C bus slave address
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Pin Descriptions (continued)
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin name SC1 DCOUT SY1 VCC2 CV1 Vin6 V6/SC5 Hin6 U6/SY5 SB5 Y6/CV5 SA5 CV1 GND1 CV2 SA3 CV3 SB3 Y7/CV4 SA4 U7/SY4 SB4 V7/SC4 SA6 Y5/CV6 SB6 U5/SY6 Hin5 V5/SC6 Vin5 Y4/CV7 Hin4 U4/SY7 Vin4 V4/SC7 Type Out Out Out SC1 signal output Output DC voltage corresponding to S2 SY1 signal output Description
Power supply 9.0 V power supply Out In In In In In In In In Ground In In In In In In In In In In In In In In In In In In In In In CV1 signal output Independent V signal input 6 V6/SC5 signal input Independent H signal input 6 U6/SY5 signal input Pin status detection for input channel 5 Y6/CV5 signal input Aspect ratio detection for input channel 5 CV1 signal input Ground CV2 signal input Aspect ratio detection for input channel 3 CV3 signal input Pin status detection for input channel 3 CV4 signal input Aspect ratio detection for input channel 4 SY4 signal input Pin status detection for input channel 4 SC4 signal input Aspect ratio detection for input channel 6 Y5/CV6 signal input Pin status detection for input channel 6 U5/SY6 signal input Independent H signal input 5 V5/SC6 signal input Independent V signal input 5 Y4/CV7 signal input Independent H signal input 4 U4/SY7 signal input Independent V signal input 4 V4/SC7 signal input
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AN15865A
Pin Descriptions (continued)
Pin No. 71 72 73 74 75 76 77 78 79 80 Pin name VCC1 G3/Y3 Hin3 B3/U3 Vin3 R3/V3 VCC4 G2/Y2 Hin2 B2/U2 Type Power supply 9.0 V power supply In In In In In G3/Y3 signal input Independent H signal input 3 B3/U3 signal input Independent V signal input 3 R3/V3 signal input Description
Power supply 5.0 V power supply In In In G2/Y2 signal input Independent H signal input 2 B2/U2 signal input
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AN15865A
Absolute Maximum Ratings
A No. 1 Parameter Symbol VCC1, VCC2 VCC3, VCC4 2 3 4 5 Supply current Power dissipation Operating ambient temperature Storage temperature ICC1, ICC2 ICC3, ICC4 PD Topr Tstg Rating 10.0 V 5.5 130 mA 23 773 -20 to +75 -55 to +125 mW C C *2 *3 *3 *1 Unit Note
Supply voltage
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 75C for the independent IC package without a heat sink. Refer to the package power dissipation prepared else and use under the condition not exceeding the allowable value. *3: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C.
Operating supply voltage range
Parameter Operating supply voltage range Symbol VCC1, VCC2 VCC3, VCC4 Range 8.5 to 9.5 V 4.7 to 5.3 Unit Note *
Note) *: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
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AN15865A
Electrical Characteristics at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V
Note) Ta = 25C2C unless otherwise specified.
B No. 1 2 3
Parameter Quiescent Current Quiescent Current Video Gain Video Frequency Response 1
Symbol ICQ12 ICQ34 GV0 GV6
Test circuits
Limits Conditions No signal input VCC1, VCC2 No signal input VCC3, VCC4 f = 500 kHz, VIN = 1 V[p-p] (except composite pass) 1.0 V[p-p] input at 30 MHz/500 kHz (during 6 dB output)(LPF OFF) 1.0 V[p-p] input at 30 MHz/500 kHz (during 0 dB output) (composite in) 1.0 V[p-p] input at 5 MHz Between contiguity channels Measure the difference from the Output DC level while in mute mode. 1.0 V[p-p] input at 6 MHz/500 kHz (LPF ON) 1.0 V[p-p] input at 10 MHz/500 kHz (LPF ON) Min 109 10 - 0.7 5.2 -1.5 Typ 118 15 - 0.2 5.7 -- Max 127 20 0.3 6.2 1.0
Unit mA mA dB dB dB
Note
1 1 1 1 1
4
fV1
5
Video Frequency Response 2
fV2
1
-1.5
--
1.0
dB
6
Crosstalk
CTV
1
--
--
-50
dB
7
Output DC level
dVDO
1
- 0.4
--
0.4
V
8
LPF characteristic1
fLPF1
1
-6
-3
0
dB
9
LPF characteristic2
fLPF2
1
--
--
-25
dB
[Hout items] 10 11 12 13 14 15 16 17 18 19 20 21 Hout1/2 high level Hout1/2 low level Hout2 pulse width(1) Hout2 pulse width(2) Hout2 pulse width(3) H pull in range upper H pull in range lower Hout2 free-run Freq.1 Hout2 free-run Freq.2 Hout2 free-run Freq.3 Hout2 free-run Freq.4 Hout2 free-run Freq.5 HHI HLO HWID1 HWID2 HWID3 fHPULLUP fHPULLLOW fHFREE1 fHFREE2 fHFREE3 fHFREE4 fHFREE5 1 1 1 1 1 1 1 1 1 1 1 1 mode 576i mode 576p, 1152i, 1152i/letter mode 1080i/50 mode 720p/50 mode 480i mode 480i, 576i mode 480p, 576p mode 1080i, 720p, 1152i, 1152i /letter 2.8 -- 1.2 0.6 520 700 -- 15.53 31.06 28.00 37.28 15.65 3.3 -- 1.6 1.0 660 -- -- 15.62 31.25 28.17 37.50 15.75 -- 0.5 2.0 1.4 800 -- - 700 15.72 31.43 28.34 37.72 15.84 V V s s ns Hz Hz kHz kHz kHz kHz kHz
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AN15865A
Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V
Note) Ta = 25C2C unless otherwise specified.
B No. 22 23 24
Parameter Hout2 free-run Freq.6 Hout2 free-run Freq.7 Hout2 free-run Freq.8
Symbol fHFREE6 fHFREE7 fHFREE8
Test circuits
Limits Conditions mode 480p mode 1 080i/60 mode 720p/60 Min 31.23 33.51 44.84 Typ 31.41 33.71 45.11 Max 31.60 33.90 45.38
Unit kHz kHz kHz
Note
1 1 1
[Vout items] 25 26 27 28 29 30 31 32 Vout1/2 high level Vout1/2 low level Vout2 pulse width(1) Vout2 pulse width(2) Vout2 pulse width(3) Vout2 pulse width(4) Vout2 pulse width(5) Vout2 pulse width(6) VHI VLO VWID1 VWID2 VWID3 VWID4 VWID5 VWID6 1 1 1 1 1 1 1 1 AFC/free mode 480i, 480p, 1080i/60 AFC/free mode 576p, 1080i/50 AFC/free mode 1152i/letter AFC/free mode 720p/60 AFC/free mode 576i, 720p/50 AFC/free mode 1152i 2.8 -- -- -- -- -- -- -- 3.3 -- 6 6 6 5 5 6 -- 0.5 -- -- -- -- -- -- V V H H H H H H
[Address Pins] 33 34 Address setting voltage (84/85hex) Address setting voltage (8C/8Dhex) VADR1 VADR2 1 1 -- 2.5 -- -- 1.5 -- V V
[DCOUT] 35 36 37 S2 compatible DC level L [00] S2 compatible DC level M [01] S2 compatible DC level H [11] VDCL VDCM VDCH 1 1 1 -- 1.4 4.0 -- -- -- 0.5 2.8 -- V V V
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AN15865A
Electrical Characteristics (continued) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter
Symbol
Test circuits
Limits Conditions Min Typ Max
Unit
Note
[I2C Interface] 38 39 40 41 Suction current during ACK SCL, SDA signal input high level SCL, SDA signal input low level Max. frequency allowable to input VACK VIHI VILO fimax 1 1 1 1 The pin voltage with Pin 3 suction current set to 3 mA during Ack. -- 3.0 0 100 -- -- -- -- 0.4 5.5 1.5 -- V V V Kbit/s
START CONDITION
SLAVE ADDRESS
ACK
SUB ADDRESS
ACK
DATA BYTE
ACK
STOP CONDITION
SDA tBUF tSU.DAT tHD.DAT tLO tSU.STO
SCL tSU.STA tHD.STA tR tHI tLO
tF
Note) The above characteristics are reference values on IC designing and not guaranteed by shipping inspection.
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AN15865A
Electrical Characteristics (Reference values for design) at VCC1, VCC2 = 9 V, VCC3, VCC4 = 5 V
Note) Ta = 25C2C unless otherwise specified.
B No. 42 43 44 45
Parameter Input Dynamic Range Mute DC level Output pedestal level Output sync level
Symbol VDYV VM VPED VSYNC
Test circuits
Reference values Conditions Min 2.4 -- 1.0 V[p-p] input 0 dB mode 1.0 V[p-p] input 0 dB mode -- -- Typ -- 3.5 3.5 3.2 Max -- -- -- --
Unit V[p-p] V V V
Note
1 1 1 1
*1 *1 *1 *1
[Hout items] 46 H VCO osc. Chara. BH 1 Conversion by 6 MHz -- -1.4 --
kHz/ mV
*1
[Vout items] 47 48 Vout2 free-run Freq.1 Vout2 free-run Freq.2 fVFREE1 fVFREE2 1 1 mode (V : 50 Hz) mode (V : 60 Hz) -- -- 50 60 -- -- Hz Hz *1 *1
[SA SB Pins] 49 50 51 52 53 Scart ident SA L Scart ident SA M Scart ident SA H Pin detect SB L Pin detect SB H VSAL VSAM VSAH VSBL VSBH 1 1 1 1 1 -- 1.7 4.0 -- 2.5 -- -- -- -- -- 1.0 3.0 -- 1.5 -- V V V V V *1 *1 *1 *1 *1
[Others] 54 55 56 57 Hin L Hin H Vin L Vin H HSL HSH VSL VSH 1 1 1 1 -- 2.5 -- 2.5 -- -- -- -- 1.5 -- 1.5 -- V V V V *1 *1 *1 *1
Note) *1 : The characteristics listed above are logical values derived from the design, and as such, all of these cannot be guaranteed. If, in the unlikely case that problems do occur related to these parameters, Panasonic will negotiate in good faith with the customer on these matters.
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AN15865A
I2C Bus Conditions
The AN15865A in I2C bus control performs switch mode selection, matrix selection, gain selection, LPF selection, synchronous mode selection and freerun mode selection through a control register and detects the system status, aspect and pin information through a status register. The upper seven address bits are allocated to the slave address while the LSB is allocated to the R/W bit. The R/W bit corresponds to the control register with with the bit set to 0 and corresponds to the status register with the bit set to 1. Sub Address 84/8C 85/8D D7 1 D6 0 D5 0 D4 0 D3 1/0 D2 1 D1 0 D0 R/W
Note) The change of D3 data is performed by control of a SLVADR terminal
Control Register The AN15865A selects slave address 84 or 8C(hex) according to the status of the SLVADR pin. Address 84(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8C(hex) will be selected with the pin grounded to the 5-V line. S Slave Address (84 or 8C) AS Sub Address (X) AS DATA (X) AS DATA (X + 1) AS DATA (X + 2) continue
Note) AS = ACK from Slave
R/W = 0 Sub Address 00 01
OUT5 sync distinction
D7
D6
D5
D4
D3
D2
D1
D0
OUT1signal select OUT3 signal select
00 : auto distinction 01 : sync on CV/Y use 10 : sync on SY use 11 : free-run 00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix
OUT2 signal select OUT4 signal select
OUT5 sync 0 : AFC 1 : independent
00 : through 01 : CCIR standard 10 : BTA standard 11 : GBR matrix Dummy sync mode Control (When 02/D7, D6 = '11')
02
free-run priority 0 : fixing 1 : auto distinction use
OUT5 signal select
000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60 SY3/SC3 GAIN 0 : 0 dB 1 : 6 dB 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50 OUT4 GAIN 0 : 0 dB 1 : 6 dB 00 : 0 V 01 : 1.9 V 10 : indefinite 11 : 4.5 V
input10 BR/UV sel 0 : BR select 1 : UV select
03
OUT4 matrix
OUT5 matrix
HVout2 polarity 0 : positive 1 : negative OUT5 GAIN 0 : 0 dB 1 : 6 dB
Field monitor sel 0 : F1 / F2 out 1 : clock moni out
04
CV1 GAIN 0 : 0 dB 1 : 6 dB OUT1 LPF 0 : through 1 : LPF ON input4 U/SY sel 0 : SY select 1 : U select
SY1/SC1 GAIN 0 : 0 dB 1 : 6 dB OUT2 LPF 0 : through 1 : LPF ON input5 U/SY sel 0 : SY select 1 : U select
CV2 GAIN 0 : 0 dB 1 : 6 dB OUT3 LPF 0 : through 1 : LPF ON input6 U/SY sel 0 : SY select 1 : U select
SY2/SC2 GAIN 0 : 0 dB 1 : 6 dB OUT4 LPF 0 : through 1 : LPF ON input7 U/SY sel 0 : SY select 1 : U select
CV3 GAIN 0 : 0 dB 1 : 6 dB OUT5 LPF 0 : through 1 : LPF ON
input8 BR/UV sel 0 : BR select 1 : UV select
05
OUT1 DCOUT
06 07 08
input9 BR/UV sel 0 : BR select 1 : UV select
Australia free-run 0 : except Australia 1 : Australia mode
test77 test87
test76 test86
test75 test85
test74 test84
test73 test83
test72 test82
test71 test81
test70 test80
Note) Please send data "00" to sub-address "07" and "08".
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AN15865A
I2C Bus Conditions (continued)
OUT1 signal select 00/D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00/D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00/D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 00/D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CV1 OUT1 CV1 IN1 CV2 IN2 CV3 IN3 CV4 IN4 SY4 + SC4 IN4 IN4 CV5 IN5 SY5 + SC5 IN5 IN5 CV6 IN6 SY6 + SC6 IN6 IN6 CV7 IN7 SY7 + SC7 IN7 IN7 DC DC DC DC DC SY1 OUT1 DC DC DC SY4 IN4 SY4 IN4 SY5 IN5 SY5 IN5 SY6 IN6 SY6 IN6 SY7 IN7 SY7 IN7 DC DC DC DC DC SC1 OUT1 DC DC DC SC4 IN4 SC4 IN4 SC5 IN5 SC5 IN5 SC6 IN6 SC6 IN6 SC7 IN7 SC7 IN7 DC DC DC DC DC *1
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AN15865A
I2C Bus Conditions (continued)
OUT2 signal select 00/D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00/D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 00/D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 00/D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CV2/SY2 OUT2 CV1 IN1 CV2 IN2 CV3 IN3 CV4 IN4 SY4 IN4 SY4 + SC4 IN4 IN4 CV5 IN5 SY5 IN5 SY5 + SC5 IN5 IN5 CV6 IN6 SY6 IN6 SY6 + SC6 IN6 IN6 CV7 IN7 SY7 IN7 SY7 + SC7 IN7 IN7 DC SC2 OUT2 DC DC DC SC4 IN4 SC4 IN4 SC4 IN4 SC5 IN5 SC5 IN5 SC5 IN5 SC6 IN6 SC6 IN6 SC6 IN6 SC7 IN7 SC7 IN7 SC7 IN7 DC *1
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AN15865A
I2C Bus Conditions (continued)
OUT3 signal select 01/D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01/D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 01/D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 01/D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CV3/SY3 OUT3 CV1 IN1 CV2 IN2 CV3 IN3 CV4 IN4 SY4 IN4 SY4 + SC4 IN4 IN4 CV5 IN5 SY5 IN5 SY5 + SC5 IN5 IN5 CV6 IN6 SY6 IN6 SY6 + SC6 IN6 IN6 CV7 IN7 SY7 IN7 SY7 + SC7 IN7 IN7 DC SC3 OUT DC DC DC SC4 IN4 SC4 IN4 SC4 IN4 SC5 IN5 SC5 IN5 SC5 IN5 SC6 IN6 SC6 IN6 SC6 IN6 SC7 IN7 SC7 IN7 SC7 IN7 DC *1
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AN15865A
I2C Bus Conditions (continued)
OUT4 signal select 01/D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01/D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 01/D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 01/D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G1/Y1 OUT4 CV1 IN1 CV2 IN2 CV3 IN3 Y7/CV4 IN4 Y6/CV5 IN5 Y5/CV6 IN6 Y4/CV7 IN7 G3/Y3 IN8 G2/Y2 IN9 G1/Y1 IN10 DC DC DC DC DC DC B1/U1 OUT4 DC DC DC U7/SY4 IN4 U6/SY5 IN5 U5/SY6 IN6 U4/SY7 IN7 B3/U3 IN8 B2/U2 IN9 B1/U1 IN10 DC DC DC DC DC DC R1/V1 OUT4 DC DC DC V7/SC4 IN4 V6/SC5 IN5 V5/SC6 IN6 V4/SC7 IN7 R3/V3 IN8 R2/V2 IN9 R1/V1 IN10 DC DC DC DC DC DC *1 HOUT1 OUT4 indefinite indefinite indefinite indefinite Hin6 IN5 Hin5 IN6 Hin4 IN7 Hin3 IN8 Hin2 IN9 Hin1 IN10 indefinite indefinite indefinite indefinite indefinite indefinite VOUT1 OUT4 indefinite indefinite indefinite indefinite Vin6 IN5 Vin5 IN6 Vin4 IN7 Vin3 IN8 Vin2 IN9 Vin1 IN10 indefinite indefinite indefinite indefinite indefinite indefinite
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AN15865A
I2C Bus Conditions (continued)
OUT5 signal select 02/D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 02/D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 02/D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 012D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G2/Y2 OUT5 CV1 IN1 CV2 IN2 CV3 IN3 Y7/CV4 IN4 Y6/CV5 IN5 Y5/CV6 IN6 Y4/CV7 IN7 G3/Y3 IN8 G2/Y2 IN9 G1/Y1 IN10 DC DC DC DC DC DC B2/U2 OUT5 DC DC DC U7/SY4 IN4 U6/SY5 IN5 U5/SY6 IN6 U4/SY7 IN7 B3/U3 IN8 B2/U2 IN9 B1/U1 IN10 DC DC DC DC DC DC R2/V2 OUT5 DC DC DC V7/SC4 IN4 V6/SC5 IN5 V5/SC6 IN6 V4/SC7 IN7 R3/V3 IN8 R2/V2 IN9 R1/V1 IN10 DC DC DC DC DC DC *1 HOUT2 OUT5 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 VOUT2 OUT5 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2
Note) *1 : 3.5 Vdc are outputted at the time of mute mode *2 : It is based on a setup of sync distinction
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AN15865A
I2C Bus Conditions (continued)
The AN15865A selects slave address 85 or 8D(hex) according to the status of the SLVADR pin. Address 85(hex) will be selected with the SLVADR pin grounded the the GND side. Address 8D(hex) will be selected with the pin grounded to the 5-V line. Status register S Slave Address (85 or 8D) AM DATA (X) AM DATA (X + 1) AM DATA (X + 2) continue
Note) AM = Ack from Master
R/W = 1 D7 D6
00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use
D5
D4
00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use
D3
D2
00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use
D1
D0
00 : 4:3 video signal 01 : 4:3 letterbox 10 : 16:9 video signal 11 : No use 100 : 576i / 50 101 : 576p / 50 110 : 1 080i / 50 111 : 720p / 50
DATA0
Aspect ratio SA3
Aspect ratio SA4
Aspect ratio SA5
Aspect ratio SA6
DATA1
Pin detect SB3 0 : Open 1 : connect Sync status 0 : 2 value 1 : 3 value
Pin detect SB4 0 : Open 1 : connect
MACRO VISION detection (OUT5) 0 : normal signal 1 : macro vision signal
Pin detect SB5 0 : Open 1 : connect auto distinc. Result CVSYdet 0 : SY 1 : CV
Pin detect SB6 0 : Open 1 : connect auto distinc. Result sync fix 0 : continue 1 : fix
AFC-LOCK OUT5 0 : unlock System status 1 : lock
Australia interlace 0 : except Australia 1 : Australia
000 : 480i / 60 001 : 480p / 60 010 : 1 080i / 60 011 : 720p / 60
DATA2
Australia format 0 : 1 152i 1 : 1 152i(letter)
Signal detect 0 : no signal 1 : signal input
0
Note) The default data at the time of power-on is 0.
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AN15865A
I2C Bus Conditions (continued)
Description of Registers 1. Control Register Out1 signal select Out2 signal select Out3 signal select Out4 signal select Out5 Sync distinction
: Selects the Input IN1 to IN7 for OUT1(CV1, SY1, SC1) (Including Mute mode) : Selects the Input IN1 to IN7 for OUT2(CV2, SY2, SC2) (Including Mute mode) : Selects the Input IN1 to IN7 for OUT3(CV3, SY3, SC3) (Including Mute mode) : Selects the Input IN1 to IN10 for OUT4(G1/Y1, B1/U1, R1/V1, Hout1, Vout1) : Switches the sync identification AFC circuit operating mode 0 = Automatic identification (with priority ranking) (If input signal to both CV and SY, SY signal will be selected) 1 = Uses CV or Y input 2 = Uses SY input 3 = Free-run : The priority of a free-run is changed 0 = Fixed mode 1 = Auto distinction will be started if a signal is inputted into a Sync block While input signal is removed, return to free-run mode. (Free-run priority only enabled when Out5 sync distinction = free-run) : Selects H, V signal of Hout2, Vout2 whether independent H and V or AFC H and V 0 = AFC H and V 1 = independent H and V : Selects the Input IN1 to IN10 for OUT5(G2/Y2, B2/U2, R2/V2, Hout2, Vout2)
Free-run priority
Out5 Sync
Out5 signal select Out4 matrix
: Selects the type of matrix conversion of Out4 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Out5 matrix : Selects the type of matrix conversion of Out5 0 = Through 1 = CCIR protocol 2 = BTA protocol 3 = Convert GBR to YUV Dummy sync mode control : Selects the type of output sync format of Out5 0 = 480i / 60 1 = 480p / 60 2 = 1080i / 60 3 = 720p / 60 4 = 576i / 50 5 = 576p / 50 6 = 1 080i / 50 7 = 720p / 50 HVout2 polarity : Select the polarity of HOUT2 and VOUT2 at AFC mode 0 = positive, Sync level is high 1 = Negative, Sync level is low
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AN15865A
I2C Bus Conditions (continued)
CV1 GAIN : Select the gain of OUT1(CV1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT1(SY1, SC1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT2(CV2) 0 = 0 dB 1 = 6 dB : Select the gain of OUT2(SY2, SC2) 0 = 0 dB 1 = 6 dB : Select the gain of OUT3(CV3) 0 = 0 dB 1 = 6 dB : Select the gain of OUT3(SY3, SC3) 0 = 0 dB 1 = 6 dB : Select the gain of OUT4(G1/Y1, B1/U1, R1/V1) 0 = 0 dB 1 = 6 dB : Select the gain of OUT5(G2/Y2, B2/U2, R2/V2) 0 = 0 dB 1 = 6 dB : This switch selects LPF on/off of OUT1 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT2 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT3 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT4 0 = Through 1 = LPF ON : This switch selects LPF on/off of OUT5 0 = Through 1 = LPF ON : Selects the DC level to OUT1(SC1) . This DC level corresponds to S2 standard. 0=0V 1 = 1.9 V 2 = indefinite 3 = 4.5 V : Selects the field distinction signal in interlace mode, or the oscillation clock of built-in VCO 0 = Field1/Field2 out (Field1 : Low Field2 : High) 1 = clock monitor out : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select
SDB00102AEB
SY1/SC1 GAIN
CV2 GAIN
SY2/SC2 GAIN
CV3 GAIN
SY3/SC3 GAIN
OUT4 GAIN
OUT5 GAIN
OUT1 LPF
OUT2 LPF
OUT3 LPF
OUT4 LPF
OUT5 LPF
OUT1 DCOUT
Field monitor select
INPUT4 U/SY select
23
AN15865A
I2C Bus Conditions (continued)
INPUT5 U/SY select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : SY input select 1 : U input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : The mode changeover switch of an incoming signal 0 : BR input select 1 : UV input select : Set up, when you oscillate the free-run of the Australia signal 0 = except Australia 1 = Australia mode : Return the control voltage of SA3(Pin 51) 0 = less than 1 V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA4(Pin 55) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA5(Pin 47) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SA6(Pin 59) 0 = less than 1V 1 = 2 V or more to less than 3 V 2 = 4 V or more 3 = indefinite : Return the control voltage of SB3(Pin 53) 0 = 5 V(Open) 1 = 0 V(Connected) : Return the control voltage of SB4(Pin 57) 0 = 5 V(Open) 1 = 0 V(Connected)
INPUT6 U/SY select
INPUT7 U/SY select
INPUT8 BR/UV select
INPUT9 BR/UV select
INPUT10 BR/UV select
Australia free-run
2. Status Register Scart Ident SA3
Scart Ident SA4
Scart Ident SA5
Scart Ident SA6
Pin detect SB3
Pin detect SB4
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AN15865A
I2C Bus Conditions (continued)
Pin detect SB5 : Return the control voltage of SB5(Pin 45) 0 = 5 V(Open) 1 = 0 V(Connected) Pin detect SB6 : Return the control voltage of SB6(Pin 61) 0 = 5 V(Open) 1 = 0 V(Connected) AFC-LOCK : Indicate the AFC lock status in the sync separation 0 = unlocked 1 = locked OUT5 System status : Return the input signal format after sync separated 0 = 480i / 60 4 = 576i / 50 1 = 480p / 60 5 = 576p / 50 2 = 1080i / 60 6 = 1080i / 50 3 = 720p / 60 7 = 720p / 50 Sync status : Return of identifying whether the input is ternary sync 0 = Binary sync 1 = Tri-level sync MACRO VISION : Indicate the whether to be a macro vision signal 0 = normal signal 1 = macro vision signal Auto Distinction Result of CV/SY detection : The detection result is indicated on which Sync shall have ridden between "CV" or "SY" 0 = SY 1 = CV Auto Distinction Result of Sync fixing situation : It indicates whether the detection result of Auto distinction fixed 0 = Under the check 1 = fixed Australia interlace : It indicates whether the input signal is Australia format 0 = except Australia 1 = Australia Australia format : It indicates the type of Australia format 0 = 1152i 1 = 1152i(litter) Signal detect : It indicates whether there is input signal 0 = no signal 1 = Signal input
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AN15865A
Test Circuit Diagram
Input 6 Input 4 Input 3 Input 2 Input 1 Input 5
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
0.47 F
54 Y7/CV4
56 U7/SY4
46 Y6/CV5
60 Y5/CV6
62 U5/SY6
64 V5/SC6
44 U6/SY5
58 V7/SC4
63 Hin5
42 V6/SC5
49 GND1
43 Hin6
50 CV2
48 CV1
55 SA4
47 SA5
53 SB3
57 SB4
41 Vin6
52 CV3
51 SA3
59 SA6
61 SB6
45 SB5
Vin5 65 Y4/CV7 66 Input 7 0.47 F Hin4 67 U4/SY7 68 0.47 F Vin4 69 V4/SC7 70 VCC1 0.47 F 71
40 CV1 10 F 39 VCC2 38 SY1 10 F 37 DCOUT 36 SC1 10 F 35 SLVADR 34 CV2/SY2 33 GND 32 SC2 10 F 31 GND2 30 CV3/SY3 29 GND 10 F 10 k Output 3 10 k 10 F 10 k Output 2 10 k 10 k 10 k 9V Output 1
Signal Generator
0.47 F 9V
G3/Y3 72 Input 8 Hin3 73 B3/U3 74 0.47 F 0.47 F 5V Vin3 R3/V3 VCC4 G2/Y2 Input 9 0.47 F Hin2 B2/U2 0.47 F 75 76 77 78 79 80 GND4 11 Sync-in 13 Vsyncsepa 14 R2/V2 16 10 F Vout2 17 10 F B2/U2 18 10 F Hout2 19 10 F G2/Y2 20 10 F GND3 21 AFC1 10 Sync-out 12 75 k Field monitor 15 SDA 3 Vin2 1 R2/V2 2 SCL 4 G1/Y1 5 Hin1 6 B1/U1 7 Vin1 8 R1/V1 9
28 SC3 10 F 27 VCC3 26 G1/Y1 10 F 25 Hout1 R1/V1 22 10 F Vout1 23 10 F B1/U1 24 10 F 10 F 10 k 10 k Output 4 10 k 5V
HV Signal Generator
4.7 k 4.7 F
10 nF
0.47 F
22 nF
10 F
0.47 F
0.47 F
0.47 F
3.3 V
0.47 F
Output 5 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k
Input 10
BUS Control
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AN15865A
Technical Data
1. Circuit diagrams of the input/output part and pin function descriptions
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No. VIN HIN
Inner circuit
Description
Pin 1, 8, 41, 65, 69, 75 Pin 6, 43, 63, 67, 73, 79
1 6 8 41 43 63 65 67 69 73 75 79
5V 75k 34k 2V 60k
Independent H, V signal input pins.
12k
200k 1k 85k 40k
2 5 7 9 44 46 48 50 52 54 56 60 62 66 68 72 74 76 78 80
G/Y B/U R/Y U/SY Y/CV
Pin 5, 72, 78 Pin 7, 74, 80 Pin 2, 9, 76 Pin 44, 56, 62, 68 Pin 46, 48, 50, 52, 54, 60, 66
9V 25 25
90k 3.7 V 4V 50 25
G/Y, B/U, R/V, U/SY, Y/CV signal input pins.
12k
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Inner circuit
Description
5V
SDA Pin 3
1.5k
50
50k 1.9 V
3
12k 90k 30k
I2C bus data input pin.
ACK
5V
SCL Pin 4
1.5k
50
50k 1.9 V
4
I2C bus clock input pin.
12k
90k
30k
5V 25
AFC1 Pin 10 10
9V 900
AFC filter pin.
12k
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Inner circuit
Description
11
GND4 Pin 11
5V system ground pin.
9V 100
Sync-out Pin 12 12 Sync signal output pin for sync separation.
12k
100
5V 60 40 3
13
1.5V
1.3 80
Sync signal input pin for sync separation.
Sync-in
Pin 13
12k
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No. V sync sepa Pin 14
5V 10 17k
Inner circuit
Description
12
14
80k 40
V sync separation filter pin.
75k 0.022 12k
Field monitor Pin 15
9V
3.3 V
15
12k
Field change signal output pin.
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Inner circuit
Description
16 18 20 22 24 26 28 30 32 34 36 38 40
G/Y B/U R/V CV/SY SC
Pin 20, 26 Pin 18, 24 Pin 16, 22 Pin 30, 34, 38, 40 Pin 28, 32, 36
9V 100
G/Y, B/U, R/V, CV/SY, SC signal output pins.
12k
100
Vout Hout 17 19
Pin 17, 23 Pin 19, 25
9V
3.3 V
AFC or independent H, V signal output pins.
12k
23 25
Independent H, V signal output pins
21
GND3 Pin 21
5 V system ground pin.
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No. VCC3 Pin 27
Inner circuit
Description
5V
CIRCUIT 5 V system power supplypin. Apply 5 V.
12k
27
29
GND
Pin 29
31
GND2 Pin 31
9 V system ground pin.
33
GND
Pin 33
5V
SLVADR 35
Pin 35
34k
75k
60k 2V
200k 12k
85k
40k
35k
Pin to output DC voltage corresponding to S2, which overlaps the SC1 signal on Output 1. The DC voltage varies with the setting in the control register.
DCOUT Pin 37 37 05/D2 0
12k 50 25
05/D1 0 1 0 1
DC value 0V 1.9 V indefinite 4.5 V
0 1 1
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No. VCC2 Pin 39
Inner circuit
Description
9V
CIRCUIT 9 V system power supply pin. Apply 9 V.
12k
39
9V 25
90k
42 58 64 70
4V
V/SC
Pin 42, 58, 64, 70
50 25
V/SC signal input pins.
12k
SB
Pin 45, 53, 57, 61
5V
45 53 57 61
200k 34k
75k
60k 2V
Pin status detection pins. Pin opened : No signal. Pin shorted : With signal. Status data is transferred to the microcomputer in serial.
12k
85k
40k
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AN15865A
Technical Data (continued)
1. Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Inner circuit
Description
5V 24k 85k 29k 3.5 V 39k 1.6 V 12k 200k 85k 85k 32k
SA 47 51 55 59
Pin 47, 51, 55, 59
34k
Aspect ratio detection pins. Pin voltage 5.0 V to 4.0 V 3.0 V to 1.7 V 1.0 V to 0 V Aspect ratio 16 : 9 Letter-box 4:3
49
GND1 Pin 49
5 V system ground pin.
VCC1 Pin 71
9V
CIRCUIT 9 V system power supply pin. Apply 9 V.
12k
71
VCC4 Pin 77
5V
CIRCUIT 5 V system power supply pin. Apply 5 V.
77
12k
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AN15865A
Technical Data (continued)
2. Notes on video gain Input Output
6 dB use 0 dB use 0 dB / 6 dB 1 V[p-p] I2C control 1 V[p-p] 2 V[p-p]
0 dB 2 V[p-p] I2C control 2 V[p-p]
For 1 V[p-p] input signal, both 0 dB and 6 dB gain can be enabled. However, for 2 V[p-p] input signal, only 0 dB gain is allowed for normal operation.
0 dB / 6 dB SY I2C control SC 0 dB / 6 dB SY + SC
The gain of SY + SC can be controlled by Control Register SY/SC GAIN. SY/SC GAIN = 0 SY + SC = -6 dB SY/SC GAIN = 1 SY + SC = 0 dB please note that the gain of SY + SC is not controlled by Control Resister CV GAIN. 3. Other supplementary matters The remedy of APL change please attach resistance of 1 M - 3 M to each pin of CV and SY between opposite GND by carrying out that it is hard to receive APL change. How to output a synchronous separation output to Hout2 to Vout2 Please choose "1" by test76(07/D6) and out5 sync(02/D4) in a control register, respectively.
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AN15865A
Usage Notes
1. For use, voltages above 5.5 V should not be applied to the following pins. (Pin No. 15, 17, 19, 23, 25) 2. Pay enough attention to that following items when using the IC, otherwise the IC may break or give off smoke. Do not insert the IC in the reverse direction. 3. Keep in mind the it may cause a latch-up by the following pins in the examination of the method of pulse current. Pin number Merit level (mA) 46 -100 47 -90 52 -80 53 -70 62 -80 Be careful not to impress the pulse current more than the above. The current level is describing the merit value of the pulse current which a latch-up does not generate. However, in all pins, a latch-up is not caused by the examination of the CV method. (200pF 200V) 4. Purchase of Panasonic I2C Components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specifications as defined by Philips.
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 JUL

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